Want a 3G-SDI SerDes Chipset that integrates both the digital SMPTE video and analog processing to off-load the demands placed on the digital processing section of the FPGA?. Gennum has products for that!

GS2972/GS2970 Serializer & Deserializer Common Features

• Operation at 270Mbps, 1.485Gbps and 2.97Gbps.
• Supports SMPTE 425M (Level A and Level B), SMPTE 424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI.
• Parallel data bus selectable as either 20-bit or 10-bit.
• GSPI host interface.
• 20-bit SDR or 10-bit DDR parallel interface options with 1.8V I/O
• 1.2V digital core supply with 1.2V and 3.3V analog supplies
• Selectable 1.8V and 3.3V I/O supplies
• Optional Level A to B and Level B to A conversion
• Both offer temperature range of -20 to +85 deg.C.
• Both packaged in 100 pin BGA (11 x 11mm).

GS2972 Serializer Key Features

• Integrated cable driver, VCO and clock cleaner.
• Integrated audio embedder for up to 8 channels of 48kHz audio.
• Ancillary data insertion.
• Optional Level A to B conversion
• Power consumption less than 405mW, including cable driver operation.

GS2970 Deserializer Key Features

• Integrated reclocker and low noise VCO supporting serial digital reclocked, or non-reclocked output.
• Integrated audio de-embedder for 8 channels of 48kHz audio with clock generator.
• Ancillary data extraction.
• Optional Level B to A conversion.
• Comprehensive error detection and correction features.
• Power consumption is typically 350mW.

GS2972/GS2970 Key Value Added Advantages

• Gennum’s 3G-SDI chipsets include all the SMPTE digital video and analog processing to off-load the FPGA from doing any “heavy lifting” e.g., SMPTE scrambling, CRC & line number insert, raster support, ANC insertion and serialization.
• Gennum offers embedded /de-embedded audio functionality such as AES, I2S and serial audio formats.
• Thanks to the integrated PLL with narrow loop bandwidth, Gennum 3G-SDI chipsets meet the SMPTE output jitter specs and are 100% production tested - not just based on product characterization.
• The GS2972 input PCLK can reject up to 300ps of jitter – difficult for FPGA’s with integrated SerDes to match this.
• The SPI host interface allows any step in the digital processing path to be disabled via programming thus giving more system flexibility for the design engineers.
• Integrated SMPTE processing on the SerDes means lower gate count FPGAs being used this lower cost, lower power consumption plus the added advantage of not requiring to port FPGA 3rd party code.
• The SMPTE output jitter requirements are <= 0.3UI and IJT industry accepted standard is >= 0.5UI. The GS29xx chipsets have output jitter = 0.2UI max and IJT = 0.7UI min.
• 1.8V I/O helps to reduce EMI with SSTL resistors that can be controlled to reduce the speed of the rising and falling signal edges.
• If embedded audio functionality is not required then Gennum’s GS2962/GS2960 3G-SDI SerDes chipset is the ideal alternative.
• Need a GS2970 deserializer with integrated cable equalizer - then choose Gennum's GS2971 3G-SDI Deserilizer.